1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a circuit for removing noise from the internal power line of a semiconductor device in order to minimize fluctuations in an internal voltage of the semiconductor device.
2. Description of the Related Art
Together with advancements in semiconductor memory design and processing techniques, semiconductor integrated circuits capable of operating at low operating voltages have been developed. For example, in dynamic random access memories (DRAMs) contained in portable electronic or/and communication equipment, the operating voltage has recently been lowered to 1.0V or less.
Each memory cell of a DRAM includes an access transistor which performs a switching function, and a capacitor (hereinafter, referred to as a cell capacitor) connected to the access transistor. Reading and writing of the DRAM is carried by selectively storing charges in the cell capacitors. Data is represented as 1 or 0 depending on the amount of charges stored in the cell capacitor. If external influences cause the amount of charges stored in the cell capacitor to vary, the data of the memory cell can be misread, resulting in a DRAM malfunction. Once source of malfunctions is the introduction of noise into the internal power line of the DRAM to such an extent that a resultant fluctuation in the power supply voltage level adversely effects the amount of charges stored in the cell capacitors.
In an effort to remove external noises, the internal power line may be equipped with decoupling capacitors. Conventional decoupling capacitors are MOS transistor type capacitors whose gates are connected to the internal power line, and whose sources and drains are coupled to a power supply ground.
FIG. 1 is a block diagram of the layout of a semiconductor memory device or chip having a conventional power noise removing circuit. The chip includes memory cells formed in each of memory cell array areas 110a, 110b, 110c, and 110d, an internal power generator 120 installed at a central region of the chip, an internal power line 130, and a plurality of decoupling capacitors MCi (where i is a positive integer) connected to the internal power line 130.
The surface area of the chip is divided into four the memory cell array areas 110a, 110b, 110c, and 110d, and each of these memory cells areas contain a plurality of sub arrays. Peripheral circuits are installed between the memory cell array areas.
The internal power line 130 has a mesh shape and is installed to supply an internal power voltage generated by the internal power generator 120 to each of the sub arrays. To reduce noise, the internal power line 130 is connected to the gate electrodes of the decoupling capacitors MCi. In FIG. 1, reference numeral 140 denotes an area where the decoupling capacitors MCi are arranged, and reference numeral 140a denotes a magnified portion of the area where the decoupling capacitors MCi are arranged.
As mentioned above, and as shown in FIG. 1, the decoupling capacitors MCi are MOS transistor type capacitors whose gates are connected to the internal power line 130 and whose sources and drains are coupled to a ground power supply.
If external noise flows into the internal power line 130, charges corresponding to the noise are stored in the MOS decoupling capacitors MCi and discharged to ground. Thus, fluctuation of the internal supply voltage is reduced.
Decoupling capacitors in the form of MOS transistors are convenient for designers to use. However, since each MOS decoupling capacitor has a low electrostatic capacity, many capacitors are needed to obtain an overall electrostatic capacity which is sufficient to remove power noise. Hence, the decoupling capacitors constitute overhead which increases the size of the chip.
In addition, current leakage through an MOS decoupling capacitor can occur if the capacitor contains a defective insulating oxide film, resulting in DRAM malfunctions. Conventional power noise removing circuits cannot completely isolate such defective decoupling capacitors from the power lines.